1. Field
Example embodiments of the inventive concepts relate to a method of designing a photomask layout, and in particular, to a method for process proximity correction, which may be performed on a target layout.
2. Description of the Related Art
With the development of photolithography technology, a scale reduction of an integrated circuit is accelerating further. For example, a pattern transferred onto a wafer may have a width less than a wavelength of an exposed beam. Accordingly, an optical proximity correction (OPC) for correcting pattern deformation caused by optical problems is recognized as being necessary to form a fine pattern having further accuracy and reliability. As fine patterns are adjacent to each other, requirements of process proximity correction for minimizing or reducing pattern deformation in an etching process are being increased along with the OPC process.
The conventional method for process proximity correction is performed on the basis of an etch bias model including information on density of neighboring patterns that are disposed in a range of several ten to several hundred nanometers around a target pattern. However, the conventional method for process proximity correction has suffered from relatively low accuracy.